Testing integrated circuits and integrated power transistors

ABSTRACT

A switching regulator that has first, second, third and fourth terminals, a first power transistor disposed between the first terminal and a first node, a second power transistor disposed between the first node and a second node, a filter including a capacitor and an inductor, and a controller. The first power transistor is partitioned into a plurality of individually-addressable first transistor segments. The second node couples the second and fourth terminals. The second power transistor is partitioned into a plurality of individually-addressable second transistor segments. The inductor is disposed between the first node and the third terminal, and the capacitor is disposed between the third and fourth terminals. The controller is operable in a plurality of modes including a normal mode in which the controller opens and closes all of the first transistor segments and all of the second transistor segments, and a test mode in which the controller opens and closes less than all of the first transistor segments and all of the second transistor segments.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to provisional U.S. ApplicationSerial No. 60/218,433, filed on Jul. 14, 2000.

BACKGROUND

[0002] The present invention relates to the design and testing of powermanagement integrated circuits.

[0003] Power amplifiers, low drop-out regulators and voltage regulatorsare examples of power management integrated circuits that include powertransistors. Voltage regulators, such as DC-to-DC converters, are usedto provide stable voltage sources for electronic systems. EfficientDC-to-DC converters are particularly needed for battery management inlow power devices, such as laptop computers and mobile phones. Switchingvoltage regulators (or simply “switching regulators”) are known to be anefficient type of DC-to-DC converter. A switching regulator generates anoutput voltage by converting an input DC voltage into a high frequencyvoltage, and filtering the high frequency voltage to generate the outputDC voltage.

[0004] Conventional synchronous switching regulators include twoswitches implemented with power transistors. One power transistor isused to alternately couple and decouple an unregulated input DC voltagesource, such as a battery, to a load, such as an integrated circuit. Theother power transistor is used to alternately couple and decouple theload to ground. An output filter, typically including an inductor and anoutput capacitor, is coupled between the input voltage source and theload to filter the output of the switches and produce the output DCvoltage. The two power transistors are typically controlled by a pulsemodulator, such as a pulse width modulator or a pulse frequencymodulator.

[0005] Performance of a switching regulator is generally affected by thecharacteristics of the power transistors. When a power transistor isopen, it is desirable to-have the power transistor operate as close toan open circuit as possible, i.e., the off-resistance of the powertransistor should be very high (ideally infinite). In the closedposition, the power transistor should act as a close to a short circuitas possible, i.e., the on-resistance of the power transistor should bevery small (ideally zero). A high on-resistance generally results inincreased power dissipation in the power transistor, degrading theefficiency of the regulator.

[0006] One of the challenges in the design of switching regulators withon-chip power transistors is the testability of the device duringmanufacturing. As just discussed, it is desireable to minimize theon-resistance of the power transistors. Unfortunately, it is difficultto obtain an accurate measurement reading of a low on-resistance value,e.g., tens of mΩ or lower, because the package lead resistance, thesocket resistance or the contact resistance of a probe during a waferprobe test or the automatic test equipment (ATE) contactor's contactresistance can be of the order of the on-resistance value. To create avoltage drop across the power transistor that is measurable at arequired degree of accuracy, a substantially large DC current has to beprovided to the power transistor. Recent automatic test equipment (ATE)testers that are designed to handle complex mixed-signal IC testing aretypically not equipped with integrated instrumentation to measurecomplex mixed-signal circuits and support high current conductionsimultaneously. In addition, the conduction of a high current throughwafer probe tips tends to wear out the hardware very quickly, resultingin production delays and increased testing cost.

[0007] Furthermore, to test the closed-loop performance of the regulatorusing ATE, large currents must be conducted through the ATE, the testprobes, and their associated parasitic inductance. Since the parasiticinductance introduced during ATE testing may be an order of magnitudelarger than that in the typical application for the regulator, largetransient voltages are created on-chip when the power transistorsswitch, leading to measurement inaccuracies and potentially evenpermanent damage to the chip.

SUMMARY

[0008] In one aspect, the invention is directed to a switching regulatorhaving first, second, third and fourth terminals, a first powertransistor disposed between the first terminal and a first node, asecond power transistor disposed between the first node and a secondnode, a filter including a capacitor and an inductor, and a controller.The first power transistor is partitioned into a plurality ofindividually-addressable first transistor segments. The second nodecouples the second and fourth terminals. The second power transistor ispartitioned into a plurality of individually-addressable secondtransistor segments. The inductor is disposed between the first node andthe third terminal, and the capacitor is disposed between the third andfourth terminals. The controller is operable in a plurality of modesincluding a normal mode in which the controller opens and closes all ofthe first transistor segments and all of the second transistor segments,and a test mode in which the controller opens and closes less than allof the first transistor segments and all of the second transistorsegments.

[0009] Implementations of the invention may include one or more of thefollowing features.

[0010] Each first transistor segment may have a source coupled to thefirst terminal, a drain coupled to the first node and a gate coupled tothe controller through a segment control line. Each second transistorsegment may have a source coupled to the first node, a drain coupled tothe second node and a gate coupled to the controller through a segmentcontrol line. The controller may operate in the normal mode in responseto a substantially constant load. The controller may be configured toswitch to the test mode in response to a request to measure anon-resistance of a power transistor. The first power transistor may be ap-channel MOSFET and the second power transistor may be an n-channelMOSFET. All of the segments may have an equivalent transistor width.

[0011] In another aspect, the invention is directed to a method formeasuring an on-resistance of a power transistor integrated onto anintegrated circuit chip. The power transistor includes a plurality ofindividually-addressable transistor segments. Less than all of thetransistor segments are closed, an on-resistance of the closedtransistor segments is measured, and an on-resistance of the powertransistor is derived from the on-resistances of the transistorsegments.

[0012] Implementations of the invention may include one or more of thefollowing features.

[0013] The transistor segments may be closed one at a time, anon-resistance of each closed transistor segment may be measured; and anon-resistance of the power transistor may be derived by averaging theon-resistances of all of the transistor segments. The transistorsegments may have an equivalent width. Each transistor segment mayinclude one or more single transistors connected in parallel.

[0014] In another aspect, the invention is directed to a method oftesting a switching regulator with a power transistor on an integratedcircuit chip for use with an application board having circuitry thatincludes a first inductor with a first inductance and a first capacitorwith a first capacitance. In the method, a power transistor including aplurality of individually-addressable transistor segments on a chip isprovided. The chip is installed on a testing board having circuitry thatincludes a second inductor with a second inductance greater than thefirst inductance and a first capacitor with a second capacitance lessthan the first capacitance. The circuit is operated with the powertransistor on the integrated circuit chip using less than all of thetransistor segments, and a closed-loop performance characteristic of theswitching regulator is measured.

[0015] Implementations of the invention may include one or more of thefollowing features. The performance characteristic may be outputvoltage, line regulation or load regulation. Measuring the lineregulation may include measuring first and second output voltages withdifferent input voltages. Measuring the load regulation may includemeasuring first and second output voltages with different load currents,e.g., a minimum load current and a modified maximum load current (thatis less than a maximum load current for the switching regulator wheninstalled on an application board). The application board may have afirst load current, and the test board may have a second load currentthat is less than the first load current. The chip may be installed onan application board having circuitry that includes the first inductorwith the first inductance and the first capacitor with the firstcapacitance. The power transistor may include N transistor segments, andthe operating step may be performed using exactly one of the Ntransistor segments. The first inductance may be L and the secondinductance may be L*N. The first capacitance may be C and the secondcapacitance may be C/N. An on-resistance of a closed transistor segmentmay be measured during operation of the circuitry, and an on-resistanceof the power transistor may be derived from the on-resistance of theclosed transistor segment.

[0016] Advantages that can be seen in implementations of the inventioninclude one or more of the following. The resistance of the powertransistors in a switching regulator can be measured accurately. Theresistance of the power transistors can be controlled more accurately,leading to more precisely control the switching timing.Switching-related losses can be reduced by decreasing the on-resistanceof the power transistors.

[0017] The details of one or more embodiments of the invention are setforth in the accompanying drawings and the description below. Otherfeatures and advantages of the invention will become apparent from thedescription, the drawings, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a schematic diagram of a switching regulator.

[0019]FIG. 2 is a circuit diagram illustrating a power transistor fromthe switching regulator of FIG. 1.

[0020] Like reference numbers and designations in the various drawingsindicate like elements.

DETAILED DESCRIPTION

[0021] In a two-switch buck-converter circuit 100 shown in FIG. 1, aswitching regulator 102 is coupled to a DC input voltage source 104,such as a battery, by an input terminal 106. The switching regulator 102is also coupled to a load 108, such as an integrated circuit, by anoutput terminal 110. The switching regulator 102 serves as a DC-to-DCconverter between the input terminal 106 and the output terminal 110.

[0022] The switching regulator 102 includes a power switch 112 and arectifier switch 116. The power switch 112 is a N-segment p-channelpower MOSFET. (“PMOS power transistor”) which alternately couples anddecouples the input terminal 106 to an intermediate node 114; therectifier switch 116 is a N-segment n-channel power MOSFET (“NMOS powertransistor”) which alternately couples and decouples the intermediatenode 114 to ground 118. The value of N—i.e., the number of segments—canbe selected by a circuit designer to achieve a desired measurementaccuracy (described below). A filter is configured to convert therectangular waveform of the intermediate voltage V_(X) at theintermediate terminal 114 into a substantially DC output voltage V_(out)at the load 108. In one implementation, the filter includes an inductor120 and an output capacitor 122.

[0023] An implementation of the rectifier switch 116 and its associateddriver circuitry is shown in FIG. 2. Each segment 200 of the rectifierswitch 116 includes an NMOS transistor 204. Although each segment Sn(i)is represented in FIG. 2 by a single NMOS transistor 204, where i=1 . .. N, integer, it should be noted that each segment Sn(i) can beimplemented by multiple single NMOS transistors connected in parallel.The segments Sn(i) are coupled such that: (a) all of the segment drainsare connected to the intermediate node 114; (b) all of the segmentsources are connected to ground 118; and (c) each of the segment gatesare isolated and driven by a separate inverter driver 206. The input ofeach inverter driver 206 is coupled to an NAND gate 208. The powerswitch 112 can be similarly implemented.

[0024] The switching regulator 102 includes a controller 124 forcontrolling the operation of the power switch 112 and the rectifierswitch 116. The controller 124 can be implemented using circuitry,software, or a combination of both. One input of each NAND gate 208 isconnected by a common control line 126 to the controller, whereas theother input of each NAND gate 208 is connected to the controller by anindividual control line 128. Each segment Sn(i) of the rectifier switch116 is coupled to the first control line 126 by a sub-control line 202.The controller 124 controls the switching of each segment Sn(i) in therectifier switch 116 by applying a common control signalCtrl(NMOS_switch) to the first control line 126 and an individualcontrol signal Ctrln(i) to each second control line 128. Thus, atransistor 204 in a specific segment turns on only when both the commoncontrol signal Ctrl(NMOS_switch) and the associated individual controlCtrln(i) are high. The switching of each segment Sp(i) in the powerswitch 112 can be similarly controlled by the controller 124 by applyinga common control signal Ctrl(PMOS switch) and an individual controlsignal Ctrlp(i).

[0025] In a normal mode of operation, the controller 124 alternatelyopens and closes all of the segments in the power switch 112 and therectifier switch 116, such that an intermediate voltage V_(X) having arectangular waveform is generated at the intermediate terminal 114. Forexample, the controller 124 sets Ctrln(1, . . . ,N)=1 and thenalternately switches between Ctrl(NMOS_switch)=1 and Ctrl(NMOS_switch)=0to alternately turn on all of the segments Sn(i) in the rectifier switch116 simultaneously and then turn off all of the segments Sn(i) in therectifier switch 116 simultaneously. Again, the power transistor 112 canbe controlled similarly.

[0026] The switching regulator 102 can be fabricated such that the powerswitch 112, rectifier switch 116, and load 108 are located on-chip(i.e., on a single chip), and the controller 124, inductor 120 andoutput capacitor 122 are discrete component located off-chip.

[0027] The performance of the switching regulator 102 is affected inpart by the characteristics of the power switch 112 and the rectifierswitch 116. For example, to achieve high power conversion efficiency inthe switching regulator 102, the on-resistance Rdson_(total) of eachswitch should be low to minimize resistive conduction losses. Theswitching regulator can be operated in a segmentation measurement testmode so that the on-resistance Rdson_(total)[measured] of each switchcan be measured. For example, assume the rectifier switch 16 (having atransistor width W_(ntotal)) is partitioned into N segments, each havingan equivalent segment width W_(ni). The ideal on-resistance Rdson_(ni)[ideal] of each segment Sn(i) is defined by:

Rdson _(ni)[ideal]=N*Rdson _(s)[ideal]

[0028] In the segmentation measurement test mode, the following stepsare performed to measure the on-resistance Rdson_(ni) [measured] of eachsegment Sn(i) of the rectifier switch 116:

[0029] 1. Close a segment. Sn(i) (e.g., to close segment Sn(2)exclusively, the controller 124 sets Ctrl(NMOS_switch)=1, Ctrln(2)=1,and Ctrln(1,3,4 . . . ,N)=0).

[0030] 2. Apply a current I_(ntest) to the closed segment Sn(i).

[0031] 3. Measure a voltage drop V_(ni) [measured] across the closedsegment Sn(i).

[0032] 4. Calculate the on-resistance Rdson_(ni) [measured] of theclosed segment Sn(i):

Rdson _(ni)[measured]=V _(ni)[measured]/I _(ntest)

[0033]  where V_(ni) [measured] is the measured voltage drop across theclosed segment Sn(i) and I_(ntest) is the amount of DC current appliedto the closed segment Sn(i).

[0034] In practice, when making a measurement Rdson_(s)[measured] of theresistance of the switch with the test equipment,

Rdson _(s)[measured]=Rdson _(s)[actual]+R[parasitic]

[0035] where Rdson_(s) [actual] is the on-resistance of the switch (withall segments closed), and Rdson [parasitic] is the unwanted resistancedue to wafer probe contact and automatic test equipment (ATE) contactresistance. However, when making a measurement Rdson_(ni)[measured] ofthe resistance of a single segment in the switch with the testequipment, it is also generally the case that

Rdson _(ni)[measured]=Rdson _(ni)[actual]+R[parasitic]

[0036] where Rdson_(ni) [actual] is the on-resistance of the segmentbased on the segment dimensions, and R[parasitic] is the unwantedresistance due to wafer probe contact and automatic test equipment (ATE)contact resistance.

[0037] Once the on-resistance Rdson_(ni) [measured] of all of thesegments Sn(i) of the rectifier switch 116 have been obtained, theaverage on-resistance Rdson_(ni)[measured]{avg} of the rectifier switch116 can be calculated:

Rdson _(ni)[measured]{avg}=(Rdson _(nN)[measured]+ . . .+Rdson_(n1)[measured])/N

[0038] We know that

Rdson _(ni)[measured]{avg}=Rdson _(ni)[ideal]{avg}+R_(i)[parasitic]{avg}

[0039] where

Rdson _(ni)[ideal]{avg}=(Rdson _(nN)[ideal]+ . . . +Rdson_(ni)[ideal])/N

and

R _(ni)[parasitic]{avg}=(R _(N)[parasitic]+ . . . +R ₁[parasitic])/N

[0040] The on-resistance Rdson_(s)[calculated] of the rectifier switch116 can be calculated from the following:

Rdson_(s)[calculated]=Rdson_(ni)[measured]{avg}/N

[0041] Since

Rdson _(ni)[measured]{avg}/N=[Rdson_(ni)[ideal]{avg}+R_(ni)[parasitic]{avg}]/N=Rdson _(s)[ideal]+[R_(ni)[parasitic]/N]

[0042] it follows that

Rdson _(s)[calculated]≅Rdson _(s)[ideal]; for large N

[0043] The value of N can be selected to achieve a desired measurementaccuracy of the voltage drops V_(ni)[measured] across the respectiveclosed segments Sn(i). Once the value of the low on-resistanceRdson_(ntotal) [measured] of the rectifier switch 116 is obtained, acomparison of the measured on-resistance Rdson_(ntotal) [measured] andthe ideal on-resistance Rdson_(ntotal) [ideal] can be made. If,Rdson_(ntotal) [measured]>>Rdson_(ntotal) [ideal], then a failureanalysis of the rectifier switch 116 can be performed by analyzing eachsegment's on-resistance Rdson_(ni) [measured]. In this manner, segmentsthat failed—i.e., segments Sn(i) havingRdson_(ni)[measured]>>Rdson_(ni)[ideal]—can be easily identified. Theon-resistance Rdson_(ptotal)[measured] of the power switch 112 can besimilarly calculated.

[0044] In high output current applications, the performance of theswitching regulator 102 can be evaluated using a closed-loopverification technique. In order to avoid the practical problemsintroduced by ATE contact inductances (e.g., large transient noiseacross the switching regulator 102), the switching regulator 102 can beplaced in a low output current test mode of operation. The closed-loopcharacteristics of the switching regulator 102 can be easily verified aslong as the loop gain and opened-loop pole locations are kept the same.In one implementation, a switching regulator 102 in the low outputcurrent test mode is configured as follows:

[0045] 1. Partition each switch into N segments having equivalentsegment widths W_(i).

[0046] 2. Close one of the N segments in each switch.

[0047] 3. Increase the value of the output filter inductor 120 by Ntimes (i.e., replace the discrete inductor component 120 having aninductance of L with a discrete inductor component 120′ having aninductance of N*L). This will also serve to reduce AC ripple currentpassing through the regulator by the factor N.

[0048] 4. Reduce the value of the output filter capacitor 122 by N times(i.e., replace the discrete capacitor component 122 having a capacitanceof C with a discrete capacitance component 122′ having a capacitance ofC/N).

[0049] 5. Reduce the tested load current range from 0-Imax to 0-Imax/N(Imax is the maximum load current for the switching regulator when usingan application board).

[0050] Specifically, a chip with the switching regulator 102 can betested by installing the chip with the power switches 112 and 116 on atest board that is identical to the application board, except for havinga discrete inductor component 120′ with an inductance of N*L (where L isthe inductance of the discrete inductor component 120 on the applicationboard) and a discrete capacitor component 122′ with an inductance of C/N(where C is the capacitance of the discrete capacitor component 122 onthe application board) and a maximum load current of Imax/N (where Imaxis the maximum load current on the application board). The switchingregulator 102 is then run using just one (or less than all) of the Nsegments. For example, in power switch 112, just one of the individualcontrol signals Ctrlp(i) is set high, the remainder of the individualcontrol signals Ctrlp(i) are set low, and the active segment iscontrolled by the common control signal Ctrl(PMOS switch). The rectifierswitch 116 can be controlled similarly. While the switching regulator isrunning, the automatic testing equipment can be used to test the voltageat various points on the circuit and perform a failure analysis.Assuming that the test is successful, the chip with the power switches112 and 116 is then installed on an application board with the discreteinductor component 120 and discrete capacitor component 122.

[0051] As part of the testing, the closed-loop performancecharacteristic of the switching regulator can be measured. Two exemplaryperformance characteristics are the line regulation and the loadregulator. To measure the line regulation, two measurements of theoutput voltage are performed. The first measurement is performed withthe minimum input voltage, and the second measurement is performed withthe maximum input voltage. The deviation between the two measurementsprovides an estimate of the line regulation when the chip is installedon the application board. To measure the load regulation, another twomeasurements of the output voltage are performed. The first measurementis performed with the minimum load current, e.g., zero, and the secondmeasurement is performed with the maximum load current, e.g., Imax/N.The deviation between the two measurements provides an estimate of theload regulation when the chip is installed on the application board.

[0052] In this manner, the combination of (3) and (5) reduces themaximum current passed through the regulator by N times, the combinationof (1), (3), and (5) reduces the voltage overstress by approximately Ntimes, and the combination of (1), (3) and (4) keeps the loop gain andopened-loop dominant pole locations nearly similar to those in theapplication circuit. By using a fraction of each switch and adjustingthe values of the external discrete output filter inductor and capacitorcomponents, the closed-loop characteristics of the switching regulator102 can be verified.

[0053] In addition, the general functionality of the various circuitblocks within the feedback control loop can be verified without havingto measure each of the individual on-chip circuit blocks separately.This results in production test-time reduction and ultimately lowermanufacturing costs.

[0054] The invention has been described in terms of particularembodiments. Other embodiments are within the scope of the followingclaims. For example, the steps of the invention can be performed in adifferent order and still achieve desirable results.

What is claimed is:
 1. A switching regulator having first, second, thirdand fourth terminals, comprising: a first power transistor disposedbetween the first terminal and a first node, the first power transistorbeing partitioned into a plurality of individually-addressable firsttransistor segments; a second power transistor disposed between thefirst node and a second node, the second node coupling the second andfourth terminals, the second power transistor being partitioned into aplurality of individually-addressable second transistor segments; afilter including a capacitor and an inductor, the inductor beingdisposed between the first node and the third terminal, and thecapacitor being disposed between the third and fourth terminals; and acontroller operable in a plurality of modes including a normal mode inwhich the controller opens and closes all of the first transistorsegments and all of the second transistor segments; and a test mode inwhich the controller opens and closes less than all of the firsttransistor segments and all of the second transistor segments.
 2. Theswitching regulator of claim 1, wherein each first transistor segmenthas a source coupled to the first terminal, a drain coupled to the firstnode and a gate coupled to the controller through a segment controlline.
 3. The switching regulator of claim 1, wherein each secondtransistor segment has a source coupled to the first node, a draincoupled to the second node arid a gate coupled to the controller througha segment control line.
 4. The switching regulator of claim 1, whereinthe controller operates in the normal mode in response to asubstantially constant load.
 5. The switching regulator of claim 4,wherein the controller is configured to switch to the test mode inresponse to a request to measure an on-resistance of a power transistor.6. The switching regulator of claim 1, wherein the first powertransistor is a p-channel MOSFET and the second power transistor is an-channel MOSFET.
 7. The switching regulator of claim 1, wherein all thesecond transistor segments have an equivalent transistor width.
 8. Amethod for measuring an on-resistance of a power transistor integratedonto an integrated circuit chip, comprising: providing a powertransistor including a plurality of individually-addressable transistorsegments; closing less than all of the transistor segments; measuring anon-resistance of the closed transistor segments; and deriving anon-resistance of the power transistor from the on-resistances of thetransistor segments.
 9. The method of claim 8, wherein: the transistorsegments are closed one at a time; an on-resistance of each closedtransistor segment is measured; and an on-resistance of the powertransistor is derived by averaging the on-resistances of all of thetransistor segments.
 10. The method of claim 8, wherein the transistorsegments have an equivalent width.
 11. The method of claim 8, whereineach transistor segment includes one or more single transistorsconnected in parallel.
 12. A method of testing a switching regulatorwith a power transistor on an integrated circuit chip for use with anapplication board having circuitry that includes a first inductor with afirst inductance and a first capacitor with a first capacitance,comprising: providing a power transistor including a plurality ofindividually-addressable transistor segments on a chip; installing thechip on a testing board having circuitry that includes a second inductorwith a second inductance greater than the first inductance and a firstcapacitor with a second capacitance less than the first capacitance;operating the circuit with the power transistor on the integratedcircuit chip using less than all of the transistor segments; andmeasuring a closed-loop performance characteristic of the switchingregulator.
 13. The method of claim 12, wherein the performancecharacteristic is output voltage.
 14. The method of claim 12, whereinthe performance characteristic is line regulation.
 15. The method ofclaim 14, wherein measuring the line regulation includes measuring firstand second output voltages with different input voltages.
 16. The methodof claim 12, wherein the performance characteristic is load regulation.17. The method of claim 16, wherein measuring the load regulationincludes measuring first and second output voltages with different loadcurrents.
 18. The method of claim 17, wherein the different loadcurrents include a minimum load current and a modified maximum loadcurrent.
 19. The method of claim 18, wherein the modified maximum loadcurrent is less than a maximum load current for the switching regulatorwhen installed on an application board.
 20. The method of claim 18,wherein the application board has a first load current, and the testboard has a second load current that is less than the first loadcurrent.
 21. The method of claim 12, further comprising installing thechip on an application board having circuitry that includes a firstinductor with a first inductance and a first capacitor with a firstcapacitance.
 22. The method of claim 21, wherein the power transistorincludes N transistor segments, and the operating step is performedusing exactly one of the N transistor segments.
 23. The method of claim22, wherein the first inductance is L and the second inductance is L*N.24. The method of claim 22, wherein the first capacitance is C and thesecond capacitance is C/N.
 25. The method of claim 12, furthercomprising measuring an on-resistance of a closed transistor segmentduring operation of the circuitry.
 26. The method of claim 25, furthercomprising deriving an on-resistance of the power transistor from theon-resistance of the closed transistor segment.